Some computer platforms conforming to, for example, Intel® Architecture-32 (IA-32) may support a feature known as Denormals-Are-Zeroes (DAZ) for handling denormal inputs or operands during execution of a program code. The platforms may include a control bit, referred to herein as a DAZ bit, which controls responses to Single Instruction Multiple Data (SIMD) instructions that are under a floating-point (FP) denormal exception condition. The program code may have one or more control instructions that control the DAZ bit in the platform. The control instructions may set the DAZ bit to one of two values, for example, “1” and “0”. When the DAZ bit is set to “1”, for example, a processor running on the platform supporting the DAZ feature may detect an instruction that raises a denormal exception condition during the code execution, and may assign denormal operands of the instruction, which is an excepted instruction, with a predetermined value, for example, zero with signs of the original operands. The processor may then execute the excepted instruction with the new value of operands. The handling of denormal operands described above may be referred to herein as a denormal input handling mechanism, or a DAZ mechanism.
A dynamic binary translator may translate a source code, for example, an IA-32 code conforming to a source architecture supporting the DAZ feature into a target code to be executed on a target platform. The target platform may have a floating-point model and therefore may be able to raise Streaming SIMD Extension (SSE) exceptions such as denormal exceptions. However, the target platform may not support the DAZ feature in handling denormal inputs of a denormal exception. One such target platform may be, for example, a platform conforming to the architecture of the Intel Itanium™ processor family.
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